1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a contact hole and a method of manufacturing the same.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is conventionally well known as a semiconductor memory which is a type of semiconductor devices. FIG. 35 is a cross sectional view showing a conventional DRAM. Referring to FIG. 35, a cross sectional structure of the conventional DRAM will be described first.
In a memory cell portion of the conventional DRAM, an isolation region 102 is provided in a prescribed region at the main surface of a silicon substrate 101. Source/drain regions 106a, 106b and 106c are formed in an active region surrounded by isolation region 102. On a channel region between source/drain regions 106a, 106b, a gate electrode 104a is formed with a gate oxide film 103 therebetween. Gate electrodes 104b and 104c are formed spaced apart from gate electrode 104a by a prescribed distance. A TEOS oxide film 105 is formed to cover the top surfaces of gate electrodes 104a to 104c. A sidewall oxide film 107 is formed to be in contact with side surfaces of gate electrodes 104a to 104c and of TEOS oxide film 105.
A silicon nitride film 108 is formed to cover TEOS oxide film 105, sidewall oxide film 107, and source/drain regions 106a to 106c. An interlayer insulating film 109 is formed on silicon nitride film 108. A bit line contact hole 160 is formed in the region of silicon nitride film 108 and interlayer insulating film 109 located on source/drain region 106b. A bit line 110a is formed to be electrically connected to source/drain region 106b through bit line contact hole 160 and to extend on the top surface of interlayer insulating film 109.
An interlayer insulating film 111 is formed on bit line 110a and interlayer insulating film 109. A capacitor contact hole 161 is formed in the region of silicon nitride film 108 and interlayer insulating films 109, 111 located on source/drain region 106a. A doped polycrystalline silicon film 112 is formed to be electrically connected to source/drain region 106a through capacitor contact hole 161 and to extend on the top surface of interlayer insulating film 111. Doped polycrystalline silicon film 112 includes a vertical part 112a electrically connected to source/drain region 106a and filling contact hole 161, and a horizontal part 112b formed integrally with this vertical part 112a and serving as a capacitor lower electrode.
A sidewall 113 of a doped polycrystalline silicon film is formed to come into contact with both side end surfaces of horizontal part 112b and to extend vertically. Sidewall 113 also serves as the capacitor lower electrode. To cover the top surface of horizontal part 112b and the surface of sidewall 113, a capacitor upper electrode 115 is formed thereon with a capacitor dielectric film 114 therebetween. Capacitor upper electrode 115 includes a doped polycrystalline silicon film. Capacitor lower electrode 112b, 113, capacitor dielectric film 114, and capacitor upper electrode 115 constitute a capacitor. An interlayer insulating film 116 is formed to cover the capacitor. On the top surface of interlayer insulating film 116, metal interconnections 118 are formed spaced apart by a prescribed distance.
On the other hand, in a peripheral circuitry portion, source/drain regions 106d and 106e are formed spaced apart by a prescribed distance at the main surface of silicon substrate 101. On a channel region between source/drain regions 106d, 106e, a gate electrode 104e is formed with gate oxide film 103 therebetween. On the region separated from gate electrode 104e by source/drain region 106d , a gate electrode 104d is formed with gate oxide film 103 therebetween. TEOS oxide film 105 is formed on the top surfaces of gate electrodes 104d and 104e. Sidewall oxide film 107 is formed to come into contact with the side surfaces of gate electrodes 104d and 104e and of TEOS oxide film 105.
Interlayer insulating film 109 is formed to cover source/drain regions 106d, 106e, sidewall oxide film 107, and TEOS oxide film 105. A contact hole is formed in the region of interlayer insulating film 109 located on source/drain region 106d and in the region of interlayer insulating film 109 located on gate electrode 104e. Inside these contact holes, an interconnection layer 110b is formed to be electrically connected to source/drain region 106d and gate electrode 104e. Here, interconnection layer 110b may be connected to either one of source/drain region 106d or gate electrode 104e. Interlayer insulating film 111 is formed to cover interconnection layer 110b, and interlayer insulating film 116 is formed to cover this interlayer insulating film 111. A contact hole is formed in the region of interlayer insulating films 111 and 116 located on a side end of interconnection layer 110b. A metal interconnection 117 is formed to be electrically connected to interconnection layer 110b through the contact hole and to extend along interlayer insulating film 116.
FIG. 36 shows a top plan layout of the entire memory cell portion of the above described conventional DRAM. Referring to FIG. 36, in the memory cell portion of the conventional DRAM, gate electrodes 104a to 104c are formed to extend in parallel, spaced apart by a prescribed distance. In a direction perpendicular to gate electrodes 104a to 104c, bit lines 110a are formed to extend almost in parallel, spaced apart by a prescribed distance. Bit line 110a is connected to source/drain region 106b in an active region 170 through bit line contact hole 160. Doped polycrystalline silicon film 112 serving as the capacitor lower electrode is connected to source/drain region 106a in active region 170 through capacitor contact hole 161.
FIGS. 37 to 53 are cross sectional views illustrating a manufacturing process of the conventional DRAM shown in FIG. 35. Referring to FIGS. 37 to 53, the manufacturing process of the conventional DRAM will be described below.
First, isolation region 102 is formed at the main surface of silicon substrate 101 in the memory cell portion, as shown in FIG. 37. On the main surface of silicon substrate 101, gate oxide films 103 are formed spaced apart by a prescribed distance. Respective gate electrodes 104a, 104b and 104c are formed on gate oxide films 103. In the peripheral circuitry portion as well, gate electrodes 104d and 104e are respectively formed on gate oxide films 103. By ion-implanting an impurity into silicon substrate 101 while using gate electrodes 104a to 104e as a mask, source/drain regions 106a to 106e are formed.
TEOS oxide film 105 is formed on the top surfaces of gate electrodes 104a to 104e. Sidewall oxide film 107 is formed to come into contact with side surfaces of gate electrodes 104a to 104e and of TEOS oxide film 105. By ion-implanting an impurity into source/drain regions 106d and 106e again, while using sidewall oxide film 107 in the peripheral circuitry portion as a mask, source/drain regions 106d and 106e of the LDD structure are completed.
Then, silicon nitride film 108 as an etching stopper layer is formed to cover the entire memory cell portion as shown in FIG. 38. Interlayer insulating film 109 including a silicon oxide film is formed to cover silicon nitride film 108 and the entire peripheral circuitry portion.
Thereafter, contact holes 109a to 109c as shown in FIG. 39 are formed by photolithography and dry etching. In etching for forming contact hole 109a in the memory cell portion, silicon nitride film 108 serves as an etching stopper layer. Then, silicon nitride film 108 in contact hole 109a is removed by etching, and bit line contact hole 160 from the top surface of interlayer insulating film 109 to source/drain region 106b is formed as shown in FIG. 40. Thereafter, interconnection layer 110 of a tungsten polyside layer, for example, is formed as shown in FIG. 41. By patterning this interconnection layer 110, bit line 110a of the memory cell portion and interconnection layer 110b of the peripheral circuitry portion are formed as shown in FIG. 42.
Then, interlayer insulating film 111 is formed to cover the entire surface, as shown in FIG. 43. As shown in FIG. 44, a polycrystalline silicon film 150 is formed on interlayer insulating film 111, and then a TEOS oxide film 151 is formed on polycrystalline silicon film 150. Thereafter, an opening 151a is formed in a prescribed region of TEOS oxide film 151.
After a TEOS oxide film (not shown) is formed to cover TEOS oxide film 151 and opening 151a, TEOS oxide film 151 is subjected to anisotropic etching to form a sidewall film 152 as shown in FIG. 45. By using the sidewall film 152 as a mask and by etching polycrystalline silicon film 150 located under the sidewall film, an opening 150a which is smaller in diameter than opening 151a by thickness of two sidewalls 152 can be formed. By anisotropic etching of interlayer insulating films 111 and 109 located below through this opening 150a, capacitor contact hole 161 as shown in FIG. 46 is formed.
Thereafter, a resist 153 is filled inside capacitor contact hole 161. This resist 153 is provided to protect the surface of silicon substrate 101 located at the bottom of capacitor contact hole 161 when polycrystalline silicon film 150 is removed by etching in a subsequent process. Polycrystalline silicon 150 is removed while this resist 153 is provided. As shown in FIG. 47, doped polycrystalline silicon film 112 is then formed filling capacitor contact hole 161 and extending along the top surface of interlayer insulating film 111. A BPSG oxide film 154 is formed on doped polycrystalline silicon film 112.
Thereafter, BPSG oxide film 154 and doped polycrystalline silicon film 112 are patterned by photolithography and dry etching to obtain the shape of the memory cell portion as shown in FIG. 48. Then, a doped polycrystalline silicon film 113 as shown in FIG. 49 is formed to cover BPSG oxide film 154 and interlayer insulating film 111. By anisotropic etching of doped polycrystalline silicon film 113, a sidewall 113a of a doped polycrystalline silicon film as shown in FIG. 50 is formed. Thereafter, BPSG oxide film 154 is removed to obtain the shape as shown in FIG. 51.
Then, as shown in FIG. 52, capacitor dielectric film 114, and doped polycrystalline silicon film 115 serving as the capacitor upper electrode are formed to cover doped polycrystalline silicon film 112, sidewall 113a and interlayer insulating film 111. By patterning capacitor dielectric film 114 and doped polycrystalline silicon film 115, the capacitor structure is then obtained as shown in FIG. 53.
Thereafter, interlayer insulating film 116 is formed on interlayer insulating film 111 of the peripheral circuitry portion and on capacitor upper electrode 115 of the memory cell portion as shown in FIG. 35. A contact hole is formed in the region of interlayer insulating films 116 and 111 of the peripheral circuitry portion located on interconnection layer 110b. Then, metal interconnection 117 is formed filling the contact hole and extending along the top surface of interlayer insulating film 116. In the memory cell portion as well, metal interconnections 118 are formed spaced apart by a prescribed distance on interlayer insulating film 116. Thus, the conventional DRAM is formed.
In the conventional DRAM shown in FIG. 35, reduction in the memory cell portion area is required as a semiconductor device is integrated to a higher degree. In this case, capacitor contact hole 161 and bit line contact hole 160 have to be formed in a very small active region. To satisfy these requirements, a technique for opening a contact hole in a self-alignment manner has been required. As such a self aligned contact opening method, a contact opening method using a silicon nitride film as an etching stopper is conventionally well known.
In the conventional structure shown in FIG. 35, bit line contact hole 160 is formed by the above mentioned self aligned contact opening method of a silicon nitride film. Specifically, as shown in FIG. 38, silicon nitride film 108 is formed and thereafter interlayer insulating film 109 of a silicon oxide film is formed thereon. By etching the portion of interlayer insulating film 109 located over source/drain region 106b while using silicon nitride film 108 as the etching stopper layer as shown in FIG. 39, contact hole 109a is formed in a self-alignment manner. Thereafter, nitride film 108 in contact hole 109a is removed to form bit line contact hole 160 as shown in FIG. 40. Conventionally, the self-aligned contact opening method using silicon nitride film 108 has been used to form bit line contact hole 160.
However, such an opening method using silicon nitride film 108 as an etching stopper layer is applicable only to a contact hole having a smaller depth as contact hole 109a shown in FIG. 39 because of following reasons. That is, although a selection ratio of a silicon oxide film and a silicon nitride film (an etching rate of the silicon oxide film/an etching rate of the silicon nitride film) is approximately 30 in theory, etching progresses faster in a stepped part than in a flat part of silicon nitride film. 108. Therefore, the selection ratio of the silicon nitride film to the silicon oxide film is reduced to approximately 10 to 15 in the stepped part.
When a contact hole having a larger depth (larger aspect ratio) like, for example, capacitor contact 161 is opened by using silicon nitride film 108 as an etching stopper layer while such a selection ratio is taken, it takes longer time to etch silicon nitride film 108 due to a process margin. Therefore, when a contact hole having a larger depth as capacitor contact hole 161 is opened, the stepped part of silicon nitride film 108 under the hole is completely scraped off and TEOS oxide film 105 located on gate electrode 104 is scraped off. Thus, that gate electrode 104c is exposed. When doped polycrystalline silicon film 112 serving as the capacitor lower electrode is formed in capacitor contact hole 161 in this case, doped polycrystalline silicon film 112 and gate electrode 104c undesirably cause a short circuit. Therefore, the self aligned opening method using silicon nitride film 108 has been adapted for forming bit line contact hole 160 having a smaller depth, and the diameter reduction process shown in FIGS. 44 to 46 has been used for forming capacitor contact hole 161.
In the above mentioned diameter reduction process, however, the number of steps is increased and the manufacturing process becomes complicated as compared with the self aligned opening method using a silicon nitride film stopper. Since reduction in contact diameter of capacitor contact hole 161 is required as a memory cell becomes smaller, it is technically difficult to form a contact hole having a larger depth and a smaller contact diameter as shown in FIG. 35.
Further, as the memory cell portion becomes smaller, the space between adjacent bit lines 160a shown in FIG. 36 becomes narrower. When the space between bit lines 110a is narrower, capacitance between bit interconnections (Cb) becomes larger, delaying data reading and writing. As a result, high speed access becomes difficult. In the conventional structure shown in FIG. 36, vertical part 112a of doped polycrystalline silicon film 112 is located between adjacent bit lines 110a. However, since the outer diameter of this vertical part 62a is small, it does not reduce capacitance between adjacent bit lines 110a. 
An object of the present invention is to provide a structure allowing easy manufacture of a capacitor contact hole and reduction in capacitance between bit interconnections in a semiconductor device.
Another object of the present invention is to form a capacitor contact hole in a self-alignment manner and to easily manufacture a structure allowing reduction in capacitance between bit interconnections, in a manufacturing method of a semiconductor device.
A semiconductor device in accordance with a first aspect of the present invention includes a pair of first and second source/drain regions, a gate electrode, a first etching stopper layer, a first interlayer insulating film, a bit line opening, a first capacitor opening, a bit line, a plug electrode, and a capacitor lower electrode. The first and second source/drain regions are formed spaced apart with a channel region therebetween at the main surface of a semiconductor region. The gate electrode is formed on the channel region. The first etching stopper layer is formed on the gate electrode and it includes an insulating film. The first interlayer insulating film is formed on the first etching stopper layer. The bit line opening is formed in the region of the first interlayer insulating film and the first etching stopper layer located on the first source/drain region. The first capacitor opening is formed in the region of the first interlayer insulating film and the first etching stopper layer located on the second source/drain region. The bit line is connected to the first source/drain region through the bit line opening. The plug electrode is connected to the second source/drain region through the first capacitor opening and formed to fill the first capacitor opening. In the plug electrode, its top surface area is larger than its bottom surface area. The capacitor lower electrode is electrically connected to the top surface of the plug electrode and formed to cover the top and side surfaces of the bit line with the first insulating film located therebetween.
In the semiconductor device in according with the first aspect, as described above, the first capacitor opening is provided in the first interlayer insulating film and the second etching stopper layer where the bit line opening is formed, and the plug electrode is filled in the first capacitor opening, so that the first capacitor opening can be formed at the same aspect ratio (depth) as the bit line opening. Therefore, the first capacitor opening can be formed by the self aligned contact opening method using the first etching stopper layer. Accordingly, the manufacturing process can be made simpler as compared with the case where the diameter reduction process is used for forming a capacitor opening, and the capacitor contact can be formed easily even if a memory cell becomes smaller. By providing the capacitor lower electrode covering the top and side surfaces of the bit line with the first insulating film located therebetween, the capacitor lower electrode is located between adjacent bit lines, allowing substantial reduction in capacitance between bit interconnections as compared with a structure where only a normal contact portion is placed between adjacent bit lines. Therefore, delay in reading and writing of data from and to a memory cell can be prevented. As a result, high speed access is allowed. In the semiconductor device, the top surface area of the plug electrode connected to the capacitor lower electrode is larger than the bottom surface area of the plug electrode connected to the second source/drain region. Therefore, a sufficient offset margin is ensured for forming the capacitor lower electrode to be connected to the top surface of the flat electrode. As a result, the process of forming the capacitor lower electrode becomes easier.
A semiconductor device in accordance with another aspect of the present invention includes a pair of first and second source/drain regions, a gate. electrode, a first etching stopper layer, a first interlayer insulating film, a bit line opening, a first capacitor opening, a bit line, a plug electrode, and a conductive layer. The first and second source/drain regions are formed spaced apart with a channel region therebetween at the main surface of a semiconductor region, and the gate electrode is formed on the channel region. The first etching stopper layer is formed on the gate electrode, and it includes an insulating film. The first interlayer insulating film is formed on the first etching stopper layer. The bit line opening is formed in the region of the first interlayer insulating film and the first etching stopper layer located on the first source/drain region. The first capacitor opening is formed in the region of the first interlayer insulating film and the first etching stopper layer located on the second source/drain region. The bit line is connected to the first source/drain region through the bit line opening. The plug electrode is connected to the second source/drain region through the first capacitor opening and formed to fill the first capacitor opening. The top surface area of the plug electrode is larger than the bottom surface area. The conductive layer has a capacitor contact portion electrically connected to the top surface of the plug electrode and extending vertically, and a capacitor lower electrode formed integrally with the top of the capacitor contact portion and extending horizontally. The capacitor contact portion of the conductive layer is formed to cover the top and side surfaces of the bit line with the first insulating film located therebetween.
In the semiconductor device in accordance with the aforementioned another aspect, the first capacitor opening is formed in the first interlayer insulating film and the first etching stopper layer where the bit line opening is formed, and the plug electrode is filled in the first capacitor opening, so that the first capacitor opening can be formed at the same aspect ratio as the bit line opening. As a result, the self aligned opening method using the first etching stopper layer can be adapted for forming the first capacitor opening. Accordingly, the manufacturing process can be made simpler as compared with the case where the first capacitor opening is formed by the diameter reduction process, and it can also easily be formed when memory cell size is smaller. By forming part of the capacitor contact portion of the conductive layer electrically connected to the top surface of the plug electrode to cover the top and side surfaces of the bit line, the capacitor contact portion is located between adjacent bit lines. Thus, the area of that portion which shields the space between adjacent bit lines is larger as compared with a conventional structure where the contact portion having a normal contact diameter is placed between bit lines. Therefore, capacitance between adjacent bit lines can effectively be prevented from becoming larger. As a result, delay in data reading and writing can be prevented, enabling high speed access. In the semiconductor device in accordance with this aspect, the top surface area of the plug electrode connected to the capacitance lower electrode is larger than the bottom surface area of the plug electrode connected to the second source/drain region. Therefore, there is a sufficient offset margin for forming the capacitor lower electrode to be connected the top surface of the plug electrode. As a result, the process of forming the capacitor lower electrode becomes easier.
In the structure of the semiconductor device in accordance with the first or another aspect, the first insulating film may include an upper insulating film formed in contact with the top surface of the bit line, and a sidewall insulating film formed in contact with side surfaces of the bit line and the upper insulating film. In addition, the top surface of the bit line may be located above the top surface of the plug electrode. By this structure, the capacitor lower electrode covering the side and top surfaces of the bit line can easily be formed.
In the structure of the semiconductor device in accordance with the first or another aspect, the surface of the capacitor lower electrode may have irregularity. By this structure, the surface area of the capacitor lower electrode is increased, allowing increase in capacitor capacitance.
In the structure of the semiconductor device in accordance with the aforementioned another aspect, a second etching stopper layer, a second interlayer insulating film, and a second capacitor opening may further be provided. In this case, the second etching stopper layer is formed on the first interlayer insulating film and the first insulating film, and it includes an insulting film. The second interlayer insulating film is formed on the second etching stopper layer. The second capacitor opening is formed in the second interlayer insulating film and second etching stopper layer to reach the first capacitor opening. Further, an end of the second etching stopper layer located between the second interlayer insulating film and the first insulating film is removed on the side of the second capacitor opening to form a concave portion over a top side end of the bit line. The capacitor contact portion is formed to fill the second capacitor opening and the concave portion and to extend over the bit line. The capacitor lower electrode is formed to extend along the top surface of the second interlayer insulating film. Thus, by forming the concave portion in the region of the second capacitor opening located over the top side end of the bit line, and filling the concave portion and the second capacitor opening with the capacitor contact portion, the capacitor contact portion covering the side end and top surfaces of the bit line can easily be formed.
A method of manufacturing a semiconductor device in accordance with yet another aspect of the present invention includes following steps. A pair of first and second source/drain regions and a gate electrode are formed at and on the main surface of a semiconductor region. A first silicon nitride film is formed to cover the gate electrode. A first interlayer insulating film of a silicon oxide film is formed on the first silicon nitride film. A first opening is formed by etching the region of the first interlayer insulating film located over the first source/drain region while using the first silicon nitride film as an etching stopper layer. By etching the first silicon nitride film in the first opening, a first capacitor opening is formed extending from the top surface of the first interlayer insulating film to the first source/drain region. A plug electrode is formed to fill the first capacitor opening and to be electrically connected to the first source/drain region. A second opening is formed by etching the region of the first interlayer insulating film located over the second source/drain region while, using the first silicon nitride film as an etching stopper layer. By etching the first silicon nitride film in the second opening, a bit line opening is formed extending from the top surface of the first interlayer insulating film to the second source/drain region. A bit line is formed to be electrically connected to the second source/drain region through the bit line opening and to extend on the first interlayer insulating film. A first insulating film is formed to cover the top and side surfaces of the bit line. A capacitor lower electrode is formed to be electrically connected to the top surface of the plug electrode and to cover the top and side surfaces of the bit line with the first insulating film located therebetween.
In the method of manufacturing in accordance with yet another aspect, the first capacitor opening is formed in the first silicon nitride film and the first interlayer insulating film where the bit line opening is formed, so that the self-aligned opening method using the first silicon nitride film as an etching stopper layer can be used for forming the first capacitor opening. Since the first capacitor opening can be formed in a self-alignment manner by using the first silicon nitride film, the manufacturing process can be made simpler as compared with the case where the first capacitor opening is formed by the diameter reduction process, and the first capacitor opening can easily be formed even if a memory cell becomes smaller. By forming the capacitor lower electrode formed on the top surface of the plug electrode to cover the top and side surfaces of the bit line, the capacitor lower electrode is located between adjacent bit lines. As a result, the semiconductor device which can reduce capacitance between bit interconnections can easily be manufactured.
A manufacturing method in accordance with a further aspect of the present invention includes following steps. A pair of first and second source/drain regions and a gate electrode are formed at and on the main surface of a semiconductor region. A first silicon nitride film is formed to cover the gate electrode. A first interlayer insulating film of a silicon oxide film is formed on the first silicon nitride film. A first opening is formed by etching the region of the first interlayer insulating film located over the first source/drain region while using the first silicon nitride film as an etching stopper layer. By etching the first silicon nitride film in the first opening, a first capacitance opening is formed extending from the top surface of the first interlayer insulating film to the first source/drain region. A plug electrode is formed to fill the first capacitor opening and to be electrically connected to the first source/drain region. A second opening is formed by etching the region of the first interlayer insulating film located over the second/drain region while using the first silicon nitride film as an etching stopper layer. By etching the first silicon nitride film in the second opening, a bit line opening is formed extending from the top surface of the first interlayer insulating film to the second source/drain region. A bit line is formed electrically connected to the second source/drain region through the bit line opening and extending on the first interlayer insulating film. A first insulating film is formed to cover the top and side surfaces of the bit line. A second silicon nitride film is formed to cover the first interlayer insulating film and the first insulating film. A second interlayer insulating film of a silicon oxide film is formed on the second silicon nitride film. A third opening is formed by etching the region of the second interlayer insulating film located on the plug electrode while using the second silicon nitride film as a mask. By etching the second silicon nitride film in the third opening, a second capacitor opening is formed extending from the top surface of the second interlayer insulating film to the top surface of the plug electrode, and a concave portion is formed in the region of the second capacitor opening located over the top side end of the bit line. A conductive layer is formed which has a capacitor contact portion filling the concave portion and the second capacitor contact, and a capacitor lower electrode extending on the top surface of the second interlayer insulating film.
According to the aforementioned further aspect of the manufacturing method, the first capacitor opening is formed in the first silicon nitride film and the first interlayer insulating film where the bit line opening is formed, so that the self aligned opening method using the first silicon nitride film as an etching stopper layer can be used for forming the first capacitor opening. Accordingly, the manufacturing process can be made simpler as compared with the case where the first capacitor opening is formed by the diameter reduction process, and the first capacitor opening can be formed easily even if a cell becomes smaller. By filling the concave portion formed over the top side end of the bit line with the capacitor contact portion, the capacitor contact portion covering the side and top surfaces of the bit line can easily be formed. Accordingly, the capacitor contact portion is located between adjacent bit lines, and the area of the portion shielding the space between adjacent bit lines is larger as compared with a conventional contact portion. Therefore, capacitance between bit interconnections can be made larger than the prior art. As a result, the semiconductor device can easily be manufactured which can prevent delay in reading and writing of data to and from a memory cell.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.